1. Field of the Invention
The present invention relates to multiphase DC/DC converters, and more particularly to adding a phase in a multiphase DC/DC converter without disturbing the output voltage.
2. Description of the Related Art
Multiphase DC/DC converters distribute current to a load among multiple phases or channels to provide increased output power and to improve efficiency at high load levels. Many electronic devices include a low-power or reduced power mode to conserve energy or battery power. The multiphase converter becomes less efficient at lower power levels while all phases remain active, so that it is desired to shut down one or more phases during lower power levels. Control logic of the device determines or detects power requirements and asserts a low power signal or the like to initiate a low power state. For example, many microprocessors detect or otherwise determine that less power is needed and that a reduced power mode of operation is advantageous. The user of an electronic device may command that the device be put in low power or standby mode. The control logic and/or microprocessor switches to low power mode if commanded or if less power is needed. To switch to low power mode, one or more phases are shut down or deactivated.
While operating in the low power mode, the control logic (automatically or in response to user input) and/or microprocessor determines that additional power is necessary and initiates the normal or high power state. In response to removal of the low power signal or any other indication that one or more phases are to be turned back on, conventional multiphase DC/DC converters simply turned on the inactive phase(s) without adjusting the remaining one or more phases already active. The sudden activation of one or more phases caused the output voltage to increase, and the feedback loop operative to maintain the output voltage level responded to the increased output voltage by adjusting the current in the remaining active phases to decrease the rising output voltage and bring it back to the target level. At the same time, the current balance loop pulled the current of each of the loops back into equality. The temporary increase in output voltage, however, often had deleterious effects on the system, and reduced overall efficiency. The current feedback loop was (and potentially still is) relatively slow so that the relative current levels were imbalanced for a significant period of time, which further reduced overall efficiency.
It is desired to avoid a significant increase in the output voltage level when adding one or more phases to achieve regular or high power mode and to balance the relative current levels of the phases without the slow current balance loop.